This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-370243, filed Dec. 4, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device using, for example, an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.
2. Description of the Related Art
In recent years, semiconductor integrated circuits have been required to consume less power and operate at higher speed. To achieve this, they have been required to operate on lower power supply voltages and have their element made finer. In this connection, SOI elements with the advantages of low parasitic capacitance and low sub-threshold coefficients have been attracting attention in place of conventional bulk elements.
In a MOS semiconductor device formed in a semiconductor layer on an insulator (hereinafter, referred to as an SOI-MOS), elements are isolated from one another by the insulating film. In contrast, in a bulk MOS semiconductor device directly formed on a semiconductor substrate, elements are isolated from one another by junction isolation. As described above, the SOI-MOS semiconductor device differs from the bulk MOS semiconductor device in configuration.
FIG. 12 shows the configuration of a general SOI-MOS. A buried oxide film 2 is formed on a silicon substrate 1 constituting an SOI substrate. On the buried oxide film 2, a semiconductor layer 3 is formed. In the semiconductor layer 3, a buried element isolation insulating film 4 made by, for example, STI (Shallow Trench Isolation). The element isolation insulating film 4 separates the semiconductor layer 3 into parts. At the surface of each separate semiconductor layer 3, a gate oxide film 5 is formed. On the gate oxide film 5, a gate electrode 6 is formed. In the semiconductor layer 3 on both sides of the gate electrode 6, source/drain regions 7 are formed. An interlayer insulating film 8 is formed on the entire surface of the SOI substrate. In the interlayer insulating film 8, gate electrodes 6 and a plurality of contacts 9 connected to the source-drain regions 7 are formed. On the interlayer insulating film 8, for example, aluminum wires 10 connected in a one-to-one correspondence to the contacts 9 are formed.
To form a mesa isolation structure made of the element isolation insulating film 4 in the SOI-MOS, a resist pattern is first formed on the semiconductor layer 3 by using lithographic techniques. With the resist patter as a mask, the semiconductor layer 3 is processed precisely, thereby producing a mesa isolation structure. The mesa isolation structure can be formed easily by using general semiconductor manufacturing processes. Therefore, the mesa isolation structure is suitable for a method of isolating elements from one another in a micro-fabricated SOI-MOS.
In the SOI-MOS with the above structure, the elements can be isolated completely. Thus, when a CMOS is configured using an SOI-MOS, a parasitic thyristor is not formed, even when the n-type region is brought close to the p-type region. As a result, not only can xe2x80x9clatch upxe2x80x9d be prevented from occurring, but also the floating capacitance can be reduced. This makes it possible to provide a highly reliable semiconductor device.
Since the SOI-MOS has the above advantages, it has lately attracted attention. It is known that, when the semiconductor layer 3 is thinned to a thickness of about 0.1 xcexcm and thin source/drain regions are formed in the semiconductor layer 3, the effect of its shape not only improves the current driving force of the SOI-MOS but also reduces the short channel effect. Consequently, the SOI-MOS is expected to be a basic structure for transistors of submicron order.
When the SOI-MOS with the above structure is formed, for example, crystal defects occur in the semiconductor layer 3. In addition, the SOI-MOS uses buried element isolation insulating films 4 made of, for example, TEOS. As a result, in the semiconductor layer 3, heavy metals acting as contaminant impurities are diffused from the element isolation insulating film 4. In the case of a bulk substrate, crystal defects and heavy metals can be removed by gettering from the back of the substrate. Since the SOI-MOS uses an SOI substrate having a buried oxide film 2, it is impossible to use a method of gettering from the back of the substrate as in the bulk substrate. This raises the subject of how to improve the reliability of the SOI-MOS.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor layer formed on a buried insulating layer on a semiconductor substrate; a plurality of element isolation insulating films which are formed in the semiconductor layer and which separate the semiconductor layer into parts; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film; diffused layers serving as source/drain regions formed in the semiconductor layer on both sides of the gate electrode; and gettering layers formed near the element isolation insulating films in the diffused layers.